CDash : UNRES

3.28s
Test: UNRES_M_MIN_prota (Passed)
Build: Linux-pgi-MPI E0LL2Y (dell15) on 2024-01-10 04:35:55
Repository revision: cfd3f3ea9ccac7a6b9cb0e802b4c9e5927a506f6
Show Command Line
Show Test Time Graph
Show Failing/Passing Graph
Test output
CTEST_FULL_OUTPUT
CTEST_FULL_OUTPUT
[dell15:140704] [[34065,0],0] ORTE_ERROR_LOG: Data unpack had inadequate space in file ../../orte/util/show_help.c at line 513
--------------------------------------------------------------------------
WARNING: Linux kernel CMA support was requested via the
btl_vader_single_copy_mechanism MCA variable, but CMA support is
not available due to restrictive ptrace settings.

The vader shared memory BTL will fall back on another single-copy
mechanism if one is available. This may result in lower performance.

  Local host: dell15
--------------------------------------------------------------------------
 thetname_pdb 
 /tmp/cdash/source/PARAM/thetaml.5parm                                                                                                                                                                                                                           
           51  opened
 thetname_pdb 
 /tmp/cdash/source/PARAM/thetaml.5parm                                                                                                                                                                                                                           
           51  opened
 MPI: node=             0  iseed=                  -3059742
 indpdb=           25  pdbref=  T
 Call Read_Bridge.
 ns=            0
 ns=            0
 after etotal
 Calling MINIM_DC
 SUMSL return code is            4  eval           760
 # eval/s    520.6624881849813     
 refstr=  T
 Processor            1  CG group            0  absolute rank            1 
  leves ERGASTULUM.
 Processor            1  wait times for respective orders order[            0 ]
    2.7144290972501040E-002  order[            1 ]   4.8688274342566729E-002 
  order[            2 ]    0.000000000000000       order[            3 ] 
    0.000000000000000       order[            4 ]    0.000000000000000      
  order[            5 ]    0.000000000000000       order[            6 ] 
    0.000000000000000       order[            7 ]   0.4232253651134670      
  order[            8 ]    0.000000000000000       order[            9 ] 
    0.000000000000000       order[           10 ]    0.000000000000000     
 Total wall clock time    1.601724892854691       sec
 Processor            0  BROADCAST time   0.1495910263620317       REDUCE time 
   3.4215029329061508E-002  GATHER time    0.000000000000000       SCATTER time
     0.000000000000000       SENDRECV    0.000000000000000       BARRIER ene 
   1.7673910129815340E-002  BARRIER grad   1.3128050602972507E-002
CG processor   0 is finishing work.
Warning: ieee_invalid is signaling
Warning: ieee_divide_by_zero is signaling
Warning: ieee_inexact is signaling
Bye Bye...
Warning: ieee_invalid is signaling
Warning: ieee_divide_by_zero is signaling
Warning: ieee_inexact is signaling
Bye Bye...
SUMSL return code 4
SUMSL return code 4
OK: absdiff= .007400, ene= -154.954800
OK: absdiff= .007400, ene= -154.954800