CDash : UNRES

3.88s
Test: UNRES_M_MIN_prota (Passed)
Build: Linux-pgi-MPI E0LL2Y (dell15) on 2023-08-30 04:14:27
Repository revision: cfd3f3ea9ccac7a6b9cb0e802b4c9e5927a506f6
Show Command Line
Show Test Time Graph
Show Failing/Passing Graph
Test output
CTEST_FULL_OUTPUT
CTEST_FULL_OUTPUT
--------------------------------------------------------------------------
WARNING: Linux kernel CMA support was requested via the
btl_vader_single_copy_mechanism MCA variable, but CMA support is
not available due to restrictive ptrace settings.

The vader shared memory BTL will fall back on another single-copy
mechanism if one is available. This may result in lower performance.

  Local host: dell15
--------------------------------------------------------------------------
[dell15:22647] [[63684,0],0] ORTE_ERROR_LOG: Data unpack would read past end of buffer in file ../../orte/util/show_help.c at line 507
 thetname_pdb 
 /tmp/cdash/source/PARAM/thetaml.5parm                                                                                                                                                                                                                           
           51  opened
 thetname_pdb 
 /tmp/cdash/source/PARAM/thetaml.5parm                                                                                                                                                                                                                           
           51  opened
 MPI: node=             0  iseed=                  -3059742
 ns=            0
 indpdb=           25  pdbref=  T
 Call Read_Bridge.
 ns=            0
 after etotal
 Calling MINIM_DC
 SUMSL return code is            4  eval           760
 # eval/s    940.8238822595711     
 refstr=  T
 Processor            1  CG group            0  absolute rank            1 
  leves ERGASTULUM.
 Processor            1  wait times for respective orders order[            0 ]
    1.0251187719404697E-002  order[            1 ]   3.5766226239502430E-002 
  order[            2 ]    0.000000000000000       order[            3 ] 
    0.000000000000000       order[            4 ]    0.000000000000000      
  order[            5 ]    0.000000000000000       order[            6 ] 
    0.000000000000000       order[            7 ]   0.2208182048052549      
  order[            8 ]    0.000000000000000       order[            9 ] 
    0.000000000000000       order[           10 ]    0.000000000000000     
 Total wall clock time    2.672829284332693       sec
 Processor            0  BROADCAST time   6.5349908545613289E-003  REDUCE time 
   1.4381268993020058E-002  GATHER time    0.000000000000000       SCATTER time
     0.000000000000000       SENDRECV    0.000000000000000       BARRIER ene 
   1.5867641195654869E-003  BARRIER grad   1.4286376535892487E-003
CG processor   0 is finishing work.
Warning: ieee_invalid is signaling
Warning: ieee_divide_by_zero is signaling
Warning: ieee_inexact is signaling
Bye Bye...
Warning: ieee_invalid is signaling
Warning: ieee_divide_by_zero is signaling
Warning: ieee_inexact is signaling
Bye Bye...
SUMSL return code 4
SUMSL return code 4
OK: absdiff= .007400, ene= -154.954800
OK: absdiff= .007400, ene= -154.954800